MAX2150ETI+T【PDF 11/15 页】IC MODULATOR I/Q WIDE 28TQFN

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Wideband I/Q Modulator with Sigma-Delta

Fractional-N Synthesizer

Table 1. Register Tables

MSB

SHIFT REGISTER DATA

Upper (MSBs) Fractional Divider Value (F) 14 Bits (Default = 8192, 10000000000000)

LSB

ADDRESS

Address

27

26

25

24

23

22

21

20

19

18

17

16

15

14

0

0

Lower (LSBs) Fractional Divider Value (F)14 Bits (Default 0 DEC, 00000000000000

Address

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

R Divider

Default = 00

CP Bleed

Default = 00

CP Current

Default = 11

Integer Divide Value (N) 8 Bits

Default = 177 DEC

Address

R1

R0

LIN1

LIN0

CP1

CP0

7

6

5

4

3

2

1

0

1

0

Reset Delay

Default = 00

Test Registers 6 Bits

Default = 0 DEC

Control Register 6 Bits

Default = 15 DEC

Address

BL1

BL0

T5

T4

T3

T2

T1

T0

INT

PD

TE

BE

XX

CPX

1

1

Table 2. Reference Divider

R1

0

0

1

1

R0

0

1

0

1

REFERENCE DIVIDE VALUE

1

2

3

4

Table 3. Integer Divider-N*

N7

0

0

—

1

1

N6

0

0

—

1

1

N5

1

1

—

1

1

N4

0

0

—

1

1

N3

0

0

—

1

1

N2

0

1

—

0

0

N1

1

0

—

1

1

N0

1

0

—

0

1

INTEGER DIVIDE VALUE

35

36

—

250

251

*N divider is limited to 35 < N < 251.

Table 4. Fractional Divider-F (Upper 14 Bits)

F27

0

0

—

1

F26

0

0

—

1

F25

0

0

—

1

F24

0

0

—

1

F23

0

0

—

1

F22

0

0

—

1

F21

0

0

—

1

F20

0

0

—

1

F19

0

0

—

1

F18

0

0

—

1

F17

0

0

—

1

F16

0

0

—

1

F15

0

0

—

1

F14

0

0

—

1

Table 5. Fractional Divider-F (Lower 14 Bits)

F13

0

0

—

1

1

F12

0

0

—

1

1

F11

0

0

—

1

1

F10

0

0

—

1

1

F9

0

0

—

1

1

F8

0

0

—

1

1

F7

0

0

—

1

1

F6

0

0

—

1

1

F5

0

0

—

1

1

F4

0

0

—

1

1

F3

0

0

—

1

1

F2

0

0

—

1

1

F1

0

0

—

1

1

F0

0

1

—

0

1

INTEGER DIVIDE

VALUE

1

2

—

268435454

268435455

______________________________________________________________________________________

11

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